Fin field effect transistors (FETs) are multi-gate devices which are widely used nowadays. FIG. 1 is a perspective view of a common type of Fin FET. As shown in FIG. 1, the Fin FET includes a substrate 10 and a fin structure 14 protruding from the substrate 10. A dielectric layer 11 is disposed to cover the substrate 10 on opposite sides of the fin structure 14 and a portion of sidewalls of the fin structure 14. A gate structure 12, including a gate dielectric layer and a gate electrode layer (not shown in FIG. 1), is disposed on the dielectric layer 11. The gate structure 12 stretches over the fin structure 14, partially covering the top surface and sidewalls of the fin structure 14. A source region and a drain region are respectively disposed within the fin structure 14 on opposite sides of gate structure 12. On the top surface and sidewalls of the fin structure 14, several regions are in contact with the gate structure 12. Therefore, multiple channel regions are formed, which may increase the drive current of the Fin FET and improve the device performance.
Conventionally, the fin structure 14 is formed by employing a lithographic process. With development of semiconductor technologies, devices and their critical dimensions are shrinking. It is therefore desirable to have high fin density of a compact device for increasing the drive current of the compact device. A high fin density means there are more fins included, and large drive current may be obtained. However, the fin density is limited by current lithographic resolution.
Therefore, there is a need to provide a fin FET including a fin structure and a method for forming the fin FET with an increased fin density.